Embodiments of present invention relate generally to three dimensional (3D) integrated circuits, and more particularly to enabling the metal-to-metal bonding of integrated circuit substrates at low temperature and pressure.
The semiconductor industry continues to drive toward greater functionality and speed of integrated circuits. For the most part, such improvements have been achieved by scaling the feature size such that more smaller devices can fit in a given area. But such scaling cannot continue indefinitely because devices are now approaching atomic dimensions. Furthermore, as the density has increased, so has the complexity and length of the interconnect circuitry, causing increases in both circuit resistance-capacitance (RC) delay and power consumption. Three-dimensional integrated circuits—that is, stacked chips bonded together—provides an opportunity to overcome these limitations.
FIG. 1 illustrates a 3D stack 100 in which two semiconductor die are bonded together. Each die may be one of a plurality of dice on a whole or partial semiconductor wafer, such that 3D stack 100 can represent any combination such as wafer to wafer, die to wafer, or die to die. A first die 110 includes a semiconductor substrate 106 in which at least one semiconductor device 101 formed and interconnect wiring layer 102, and a second die 120 includes one or more TSVs (through substrate vias) 121 for passing power or signals entirely through the second die 120 to the devices 101 of the first die. The interconnect wiring 102 is embedded in back end of the line (BEOL) dielectric layers 103, formed on substrate 106. The interconnect wiring and TSVs include a conductive core, which can be formed of copper. The core is typically separated from the surrounding materials (e.g., the substrate wafer or dielectric layers) by liner and barrier layers.
The wiring and TSVs are conventionally formed by plating copper onto a seed layer that has been deposited such as by PVD or ALD. The grain size of the plated copper depends on the plating conditions and the thickness of the deposition. This microstructure is known to “self-anneal”, that is, the thermodynamics favor grain growth, even at room temperature, and even though this grain growth induces a tensile stress. See Lee and Wong, “Correlation of stress and texture evolution during self- and thermal annealing of electroplated Cu films”, J. Appl. Phys 93:4 3796-3804. Such stresses can cause distortions such as warpage of a silicon wafer. Typical semiconductor processing includes a thermal anneal to accelerate the atomic rearrangement and bring the plated copper to an equilibrium state.
Controlling the anneal enables further high fidelity processing such as alignment and bonding of two substrates to form the 3D stacked structure of FIG. 1. First die 110 (after completing BEOL processing to form layer 103 with interconnect wiring 102) and second die 120 can be bonded by thermocompression bonding between a plated metal (e.g., 105) on the bonding surface 104 of the first die and a plated metal (e.g., 125) on the bonding surface 124 of the second die. This method may be used in die to die, or die to wafer, as well as for wafer to wafer bonding for 3D applications. The facing surfaces of the two die can be formed with metal regions, for example, a mirror image pattern of copper regions as depicted in FIG. 2. These metal regions can constitute part of the circuitry of the final 3D stack, or they can be created strictly as bonding regions. Metal bonding to form the 3 C integrated circuit stack can be achieved by holding the stack together at temperature of at least 350-400 C for at least 30 to 60 minutes.
Unfortunately, such conditions can exceed the thermal budget of delicate integrated circuitry which cannot be exposed, or at least not for extended time, to high temperature. Farrens reports in “Wafer and Die Bonding Technologies for 3D Integration”, MRS Fall 2008 Proceedings E, that lower temperature atomic diffusion of all fcc metals is primarily along grain boundaries. Bonding a 3D stack at lower temperatures would permit a wider selection of devices and materials, but has not been possible because, as noted above, conventional processing promotes grain growth such that a plated copper surface has a very low concentration of grain boundaries. Even without a thermal anneal, thermodynamics drives grain growth and within a very short time converts the surface microstructure of plated copper such that metal to metal bonding at temperature below 350 C is impractical.
A need remains to achieve reliable metal bonding in reasonable time at less stressful conditions.